Electromagnetic shield for testing integrated circuits

ABSTRACT

An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

PRIORITY CLAIM

The instant application claims priority to Italian Patent ApplicationNo. MI2009A001511, filed Aug. 28, 2009, which application isincorporated herein by reference in its entirety.

TECHNICAL FIELD

An embodiment of the present invention relates to systems for testingIntegrated Circuits (IC), and particularly an embodiment relates toprobe cards for testing IC's through Radio Frequency (RF) signals.

BACKGROUND

IC's are typically manufactured in the form of dies on a wafer ofsemiconductor material. Particularly, after the manufacturingoperations, the semiconductor material wafer is subdivided into dies,each one including a respective IC.

Before being packaged and sent to customers, and before being installedin complex electronic systems, the ICs are tested for evaluating theirfunctionality, and particularly for assuring that they are notdefective. During the test, information may be retrieved regardingglobal or local physical faults (such as, for example, the presence ofundesired short circuits and break) and more generally regarding the ICoperation on each tested die (for example, checking the waveforms of oneor more output signals generated by the IC on each tested die). In thisway, the subsequent phases of the manufacturing process (such as forexample the linking of the bond wires, the packaging, and the finaltest) may be carried out only by the dies which have met predeterminedresults.

According to a known test technique, the dies including the ICs aretested before the semiconductor material wafer is subdivided. A testperformed at wafer-level is denoted “wafer sort” or Electrical WaferSort (EWS).

In order to perform the test, a test apparatus is employed, whichcomprises a tester coupled to the semiconductor material wafer includingthe dies to be tested by means of a proper probe card.

The tester is adapted to manage signals to be used for performing thetest; in the following, such signals will be denoted “test signals”. Thetest signals include test stimula (such as, commands, memory locationaddresses, data to be written in the memory device) generated by thetester and sent to each die to be tested through the probe card, andtest response signals, which are generated by the ICs integrated in eachdie during the test phase in response to the received test stimula. Thetest response signals are sent by the IC integrated in each die to thetester through the probe card; such signals are then processed by thetester in order to obtain an indication regarding the correct (orincorrect) operation of the ICs integrated in the dies.

In order to allow the exchange of the test signals, the probe card iselectrically coupled to the dies by means of particular probes.Particularly, the probe card consists of a Printed Circuit Board (PCB)connected to a plurality of mechanical probes adapted to physicallycontact input/output contact pads included in the die to be tested.

Each input/output contact pad is formed by an enlarged metallizationregion surrounded and possibly partially covered by a passivation layer.

During the test operations, the contact pad is etched or scratched bythe mechanical action exerted by the probe's tip to establish a goodelectrical connection. In this way, it is possible to allow the testsignals to be exchanged between the tester and the die to be tested.

A first category of known probe card comprises the probe cards providedwith so-called cantilever probes. Such probes comprise a ring (forexample, made of aluminum, special alloys, or ceramic material) which isconnected to an epossidic support. Such epossidic support is adapted tosupport a plurality of test elements comprising elastic cantileverprobes, formed by an alloy having good electrical and mechanicalproperties. Particularly, each cantilever probe includes a beam having afirst end connected to the epossidic support and a second end includinga tip, which in use it is intended to be forced against a contact pad ofthe die including the IC to be tested.

As an alternative to the probe cards including cantilever probes, it ispossible to provide substantially vertical probes comprising conductivewires which pass through holes formed in a head of the probe card. Indetail, the head of the probe card includes an upper guide plate stackedon a lower guide plate. Each probe has a tip that protrudes from thelower guide plate and it is adapted to electrically contact thecorresponding contact pad of the die to be tested. A contact interfaceknown as “space transformer” is connected to the upper guide plate andis adapted to electrically couple the probes to the printed circuitboard in such a way to allow the signal exchange between the tester andthe die to be tested.

A further type of probe card provides for the use of probes of themicroelectromechanical type (known as MicroElectroMechanical Systemprobes, or MEMS probes). With the term of MEMS probe it is intended aprobe that has been manufactured through lithographic processes similarto those used for manufacturing the ICs. Thanks to the use of suchlithographic processes, it is possible to manufacture a great number ofMEMS probes having sufficiently homogeneous structural and electricalfeatures in a manner that is relatively cheap.

Among the various known topologies of MEMS probes for the use in theintegrated-circuits probe card field, one of the most widespread isformed by an elastic metallic beam having an end that is connected to asubstrate (for example, made of a semiconductor or ceramic material) bymeans of one or more conductive-material support pillars, and the otherend to a protruding tip adapted to electrically contact the contact padsof the die to be tested. The substrate is provided with properconductive tracks connected to the support pillars. In this way, theexchange of test signals between the generic die and the tester by meansof a MEMS probe may be carried out through a conductive path comprisingthe tip, the elastic beam, the support pillars and the conductive tracksformed in the substrate.

Further equivalent types of MEMS probes are known such as for exampleprobes formed by a single metallic beam properly shaped which isdirectly connected to the substrate, probes formed by a stringy elasticelement connected to the substrate and provided with a laminar tip,probes comprising silicon beams, and probes formed by thin curved foilsof a conductive material.

If the ICs formed on the semiconductor material wafer comprise circuitsintended to be exploited at the Radio Frequencies—in jargon, RFcircuits—the testing provides for the use of Radio Frequency testsignals—briefly, RF signals. For this purpose, the tester is capable ofgenerating and acquiring RF signals, and the probe card is capable ofproviding and retrieving such RF signals to/from the ICs to be testedthrough the probes.

However, it is known that the management of RF signals may be critical,and may require one to employ a higher level of care with respect tothat required for managing more slowly varying signals, i.e.,low-frequency signals. Indeed, considering the generic conductive pathof the probe card adapted to convey test signals from the tester to theprobes contacting the ICs to be tested (and vice versa), such path, inthe case of relatively low frequency test signals, may be assimilated toa short circuit, while, in the case of RF test signals, the sameconductive path may behave as a transmission line. Consequently, inorder to test RF circuits, one accurately designs the probe card, takinginto account all the electromagnetic issues due to the presence of thetransmission lines. For example, the probe cards presently employed fortesting ICs by means of RF test signals comprise a plurality of properexpedients, such as coaxial cables and connectors, wide ground planesfor the electromagnetic shielding, and so on.

However, although such solutions may be capable of efficiently shieldingthe transmission lines formed on the probe card, the correct carryingout of the test operations may not reach a successful conclusion becauseof the crosstalk phenomena that would occur between the probes connectedto the probe card. Particularly, each probe, when in the path of an RFsignal, behaves as an antenna irradiating electromagnetic waves in thesurrounding area; such irradiated electromagnetic field may be picked upby the near probes of the probe card, negatively interfering with thesuccessful conclusion of the test operations.

Among the solutions presently employed for resolving such problem, it isknown to reduce the effects due to the crosstalk phenomenon by means ofa proper design of the probes (regardless of the type) to diminish theirradiated electromagnetic field. For example, according to a knownsolution the electromagnetic field irradiated by a probe is reduced bydiminishing as much as possible the length of the probe itself; however,by employing a solution of such type, it is possible to incur indrawbacks of other types, since a probe card equipped with probes thatare too short may cause problems during the portion of the test phasewhich provides for the alignment of the probes to the pads of the IC tobe tested.

In view of the above, when ICs formed on a semiconductor material waferare to be tested by means of RF test signals, presently it may bepreferred to test a single IC at a time, so as to avoid the arise ofcrosstalk phenomena among probes directed to contact different ICs.However, employing a solution of such type jeopardizes the possibilityof testing more than one IC at the same time, consequently increasingthe cost of the test operations in a non negligible way compared toparallel testing.

SUMMARY

An embodiment of the present invention overcomes the previouslymentioned drawbacks.

An embodiment of the present invention relates to a probe card. Theprobe card comprises a plurality of probes. Each probe is adapted tocontact a corresponding terminal of a circuit integrated in at least onedie of a semiconductor material wafer during a test phase of the wafer.Said plurality of probes includes at least one probe adapted to provideand/or receive a radio frequency test signal to/from the correspondingterminal. Said probe card comprises at least one electromagnetic shieldstructure corresponding to the at least one probe adapted to provideand/or receive the radio frequency test signal for the at least partialshielding of an electromagnetic field irradiated by such at least oneprobe adapted to provide and/or receive the radio frequency test signal.

An embodiment of the present invention regards the use of a probe card.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments of the invention, and features and advantagesthereof, will be best understood by reference to the following detaileddescription, given purely by way of a non-restrictive indication, to beread in conjunction with the accompanying drawings. In this respect, itis expressly intended that the figures are not necessary drawn to scaleand that, unless otherwise indicated, they are merely intended toconceptually illustrate the structures and procedures described herein.

FIG. 1 schematically shows a sectional view of a portion of anembodiment of a piece of test equipment comprising a probe card for theelectrical coupling with a semiconductor wafer to be tested; and

FIGS. 2A, 2B, 2C, 3, 4A, 4B, 5, 6, 7A, 7B, 7C, 8A, 8B, 9, 10A, 10B, 11,12A, 12B, 13, 14A, 14B and 14C show electromagnetic shield structuresaccording to various embodiments of the present invention.

DETAILED DESCRIPTION

With reference to FIG. 1, it is schematically illustrated a sectionalview of an embodiment of a portion of a piece of test equipment 100comprising a probe card 105 adapted to electrically couple IntegratedCircuits (IC) in dies 102 of a semiconductor material wafer 110 to betested.

The wafer 110 is located on a support 115 capable of being moved alongthe three orthogonal directions “x”, “y” and “z” schematically indicatedin figure; the support 115 may be further rotated and inclined. Once thesemiconductor wafer 110 has been placed on the support 115, the latteris moved in such a way to bring the wafer 110 to be tested in contactwith the probe card 105.

In the example at issue, the probe card 105 includes a printed circuitboard 125 connected to a (e.g., semiconductor or ceramic) substrate 130.The substrate 130 supports a plurality of probes 135, for example probesof the MEMS type, adapted to electrically contact pads 137 formed on thedies 102 of the wafer 110 to be tested.

The printed circuit board 125 comprises the circuits required for thecommunication between a tester (not shown in the figure) and the wafer110 to be tested. For example, the printed circuit board 125 comprisescircuits for processing data/signals controlling the whole operation ofthe probe card 105, and that may operate under the control of a softwarestored in a memory unit (for example, one or more memories included inthe printed circuit board 125).

Although in the considered example the probes 135 are supported by asubstrate 130, in another embodiment the probes 135 may be directlyconnected to the printed circuit board 125.

Particular or “fiducial” marks 140 may be provided on the printedcircuit board 125 or on the substrate 130 for allowing the correctalignment between the probe card 105 and the wafer 110.

The probes 135 are arranged on the substrate 130 in such a way each oneof them is adapted to establish a communication relationship with arespective pad 137 of a die 102 of the wafer 110 to be tested. In thisway, the probe card 105 is capable of providing the test signalsgenerated by the tester to the circuits integrated in the dies 102, andthe tester is capable of receiving corresponding signals generated bythe circuits integrated in the dies 102 in response to such testsignals.

A particular of the wafer 110 surface is shown in the figure with thereference 145, and particularly a portion of the wafer 110 surfacecorresponding to a generic die 102. As can be seen in the figure, eachdie 102 is arranged on the wafer 110 surface at a predetermined distancefrom the adjacent die 102, in such a way to form semiconductor materialseparation lines (in jargon, “scribe lines”), identified in figure withthe generic reference 150. At the end of the manufacturing process andafter the test has been completed, the die 102 are separated from thewafer 110 by means of the action of a diamonded saw or a laser alongsuch scribe lines 150.

According to an embodiment of the present invention, the testing of thecircuits integrated in the dies 102 by means of RF test signals may becarried out in parallel on more than one die 102 at the same time sincethe probe card 105 is provided with electromagnetic shield structuresadapted to shield (or at least reduce) the electromagnetic fieldirradiated by the probes 135.

According to an embodiment of the present invention, suchelectromagnetic shield structures are proper probes—referred to asshielding probes and identified with the generic reference 205—biased toa constant potential, such as the ground potential, trough a propertransmission line. The shielding probes 205 may be of the same type ofthe probes 135 used for providing and/or receiving the test signalsto/from the die 102, and are connected to the probe card 105 in a verysimilar way (in the example at issue, supported by the substrate 130).Unlike the probes 135 used for the test signals, which are arranged onthe substrate 130 in such a way that each one of them is adapted toestablish a communication relationship with a respective contact pad 137of a die 102 of the wafer 110 to be tested, the shielding probes 205 arearranged on the substrate 130 for forming electromagnetic shieldsadapted to shield the electromagnetic shield irradiated by the probes135 from RF test signals irradiated by probes or other dies.

In this way, as illustrated in FIG. 2A, according to an embodiment ofthe present invention it is possible to shield two adjacent die 102 onthe wafer 110 reducing as much as possible the crosstalk phenomenaoccurrences among probes 135 adapted to contact the pads 137 of the twodie 102 for providing and/or receiving RF test signals. Particularly, inthis case the shielding is obtained by means of an array of shieldingprobes 205 arranged on the substrate 130 in such a way that eachshielding probe 205 belonging to such array is positioned incorrespondence to the scribe line 150 which divides the two adjacentdies 102 when the wafer 110 is brought in contact with the probe card105 during the test.

Biasing such shielding probes 205 with a direct voltage such as theground voltage (or ground potential), the propagation of the electricfield irradiated by a probe 135 (crossed by an RF test signal)contacting a pad 137 of one of the two dies 102 toward the probes 135contacting the pads 137 of the other die 102 is strongly reduced. Inthis way it is possible to perform the test in parallel, providing RFtest signals to circuits integrated in both the adjacent dies 102,without having to incur a crosstalk phenomena capable of compromisingthe successful conclusion of the test.

According to an embodiment of the present invention, the voltages forbiasing the shielding probes 205 are provided by the tester by means ofproper transmission lines on the probe card 105, like the test signals.

In order to correctly operate as an electromagnetic shield toward theelectromagnetic fields generated by the passage of an RF signal in aprobe 135, it is not necessarily that the shielding probes 205 arebiased with a constant potential. Indeed, it is possible to obtain ananalog shielding effect by biasing the shielding probes 205 by means ofa potential whose value varies at a frequency that is sufficiently lowerthan the frequency of the RF signal that has generated the field to beshielded.

Moreover, it is not necessary that all the shielding probes are biasedto the same potential value; indeed, similar considerations apply to thecase in which each shielding probe 205, or each group of shieldingprobes 205, is biased by means of a different voltage value.

According to an embodiment of the present invention illustrated in FIG.2B, the length of the shielding probes 205 is such to leave a spacebetween the tip of each shielding probe 205 and the surface of theunderlying scribe line 150 (more in particular, the passivation layer210 located over the surface) when the probe card 105 is placed incontact with the wafer 110 during the test. However such solution maynot be advisable, since usually it may be preferred to form the probecards 105 in such a way that all the probes are planar to each other.

For this purpose, in an embodiment, each shielding probe 205 may have alength that is sufficient to establish a physical contact between thetip of the shielding probe 205 and the passivation layer 210 over thesurface of the scribe line 150 during the testing, as illustrated inFIG. 2C. Even if in this way it is possible to damage the scribe line150 because of the direct mechanical contact between the tip of theshielding probe 205 and the scribe line 150, the correct operation ofthe circuits integrated in the die 102 is not affected, since the scribelines 150 are destined to being subjected to the cutting operationsafter the testing operations.

According to an embodiment of the present invention, in order to shieldthe probes 135 adapted to enter in communication with the contact pads137 of a die 102 from the electromagnetic fields irradiated by probes135 adapted to enter in communication with the contact pads 137 of oneor more of the dies 102 adjacent to such die 102 in the wafer 110,during the testing each side of such die 102 is surrounded by arespective array of shielding probes 205, as illustrated in FIG. 3.

As illustrated in FIG. 4A, by arranging the shielding probes 205 on thesubstrate 130 of the probe card 105 according to matrix arrangementcorresponding to the scribe lines 150 of the wafer 110 to be tested, itis possible to surround completely each die 102 of the wafer 110 withshielding probes 205, and to perform the test on all the dies 102 of thewafer 110 at the same time.

According to a further embodiment of the present invention, it ispossible to provide for an intermediate solution, in which the shieldingprobes 205 are arranged on the substrate 130 of the probe card 105 insuch a way to surround only a subset of the die 102 of the wafer 110 atthe same time. This embodiment implies a reduction of the test's degreeof parallelism (the die 102 are not tested all at the same time) butallows to simplify the structure of the probe card 105, providing for alower number of shielding probes 205. Moreover, if the shielding probes205 are arranged on the substrate 130 in such a way to surround die 102that are not adjacent to each other (as it is illustrated in FIG. 4B),it is possible to further reduce the crosstalk phenomenon.

In some cases, it is possible that the wafer 110 is provided withcontact pads directly located within the scribe lines 150. Unlike thecontact pads 137 formed within the dies 102, some of the contact padsformed in the scribe lines 150 may be only exploited during the test—forreceiving and transmitting from/to the probes 135 the test signals—andnot during the standard operation of the circuits integrated in the die102. If during the test such contact pads located within the scribelines 150 are coupled with probes 135 conveying signals whose potentialvanes at a frequency that is sufficiently lower than the frequency ofthe RF signals, such probes 135 may contribute to the formation of theelectromagnetic shields, acting both as a normal test probe and as ashielding probe. Alternatively, such probes as well may be biased in ananalogous way as previously recited.

According to an embodiment of the present invention, the scribe lines150 are provided with contact pads that are specifically destined toenter in contact with a respective shielding probe 205 during the test.Such contact pads, denoted shielding contact pads, are identified inFIG. 5 with the numeral reference 505. Thanks to the presence of suchshielding contact pads 505, possible scribe line 150 damages may beprevented, since a final customer interested in the direct acquiring ofthe wafer 110 may request substantially undamaged scribe lines 150.

In all the previously described embodiments, the shielding probes 205are biased by the tester through the probe card 105. As a consequence,the probe card 105 exhibits an additional complexity level, given by theneed to distribute the various biasing voltages to the shielding probes205; the higher the number of shielding probes 205 arranged on thesubstrate 130, typically the more complex the probe card 105.

According to an embodiment of the present invention, this problem may beresolved by connecting multiple shielding contact pads 505 to each otherthrough a conductive connection track, functioning as a transmissionline, which lies in the space of the scribe lines 150. In this way it ispossible to leave floating from an electrical point of view one or moreshielding probes 205 of the probe card 105, and bias them by exploitingthe conductive connection line, thus simplifying the structure of theprobe card 105.

For example, according to an embodiment of the present inventiondescribed in FIG. 6, at least one die 102 is surrounded by shieldingcontact pads 505 on each side (i.e., in the scribe line portions 150extending adjacent to the die); a portion of such shielding contact pads505 (in the example at issue, corresponding to three sides of the die102) is connected to a same conductive connection line, identified withthe reference 605. One of the shielding contact pads 505 linked to theconnection line 605 is further linked to a contact pad 137 within thedie 102 (through a link that is considered to be part of such connectionline 605, and identified in FIG. 6 with a dotted line) adapted to becontacted during the testing by a probe 135 that provides a constant(such as the ground potential) or a slowly variable potential. In thisway, such potential may propagate along the connection line 605, andbias all the shielding probes 205 which are in contact with theshielding contact pads 505 linked to such connection line 605. As aconsequence, it is not required to bias the shielding probes 205 withthe tester through the probe card 105. The shielding probes 205 may thusbe left floating from the electrical point of view in the probe card105, since their biasing through the tester is no longer required. Aspreviously mentioned, some contact pads located in the scribe lines 105may be exploited during the test phase for receiving and/or providingtest signals; in this case, such pads are not connected to theconnection line 605.

Examples of connection line 605 and shielding contact pad 505 accordingto embodiments of the present invention will be disclosed in thefollowing figures; such figures are sectional views of a portion of thewafer 110 during the test operations, showing a generic shielding probe205 and the probe 135 adapted to contact the contact pad 137 of the die102 which provides the constant or slowly variable potential used forbiasing the connection line 605.

Particularly, according to embodiments illustrated in FIG. 7A, both theconnection line 605 and the shielding connection pad 505 are directlyformed over the passivation layer 210, with the connection line 605implemented by means of a metallic material line.

According to an embodiment of the present invention illustrated in FIG.7B, the shielding contact pad 505 is implemented in the same way as thecontact pads 137, but is directly generated in the scribe line 150.

According to the embodiment illustrated in FIG. 7C, the connection line605 is generated by means of a metallic conductive layer under the wafer110 surface, using for example one of the “metal lines” used for formingconductive tracks within the integrated circuits of the die 102 whichcrosses the seal ring (not illustrated in figure) surrounding such die102.

Without descending into exceedingly specific details, the connectionline 605 may be formed over the passivation layer 210, and at the sametime the linking between such connection line 605 and the contact pad137 of the die 102 that provides the constant or slowly variablepotential may be formed by means of a metallic conductive layer underthe wafer 110 surface; vice versa, the connection line 605 may be formedunder the wafer 110 surface while the linking between such connectionline 605 and the contact pad 137 of the die 102 providing the constantor slowly variable potential may be formed over the passivation layer210.

Although reference has been made to an open loop connection line 605adapted to be biased by means of the linking to a single contact pad 137of the die 102, similar considerations apply to the case in which suchconnection line 605 is linked to more than one contact pad 137 of thedie 102 (for example to two pads, as illustrated in FIG. 8A) and/or theconnection line 605 is of the closed loop type (as illustrated in FIG.8B). In this case, the constant or slowly variable potential used tobias the connection line 605 may be fed through at least one shieldingprobe 205. The ring formed by the connection line 605 may be possiblyprovided with one or more interruptions for the purpose of avoiding theformation of a closed path capable of causing the passage of a current.

FIG. 9 is a top view of a portion of the wafer 110 surface in which theconnection lines 605 and the shielding contact pads 505 corresponding tomore dies 102 are shown, in the case in which each contact line 605 isof the closed loop type.

According to an alternative embodiment of the presentinvention—illustrated in FIG. 10A and FIG. 10B—, the shielding contactpads 505 are arranged on the wafer 110 partially within the area of thedie 102, and partially over the scribe line 150.

One or more embodiments of the present invention may be also applied tocases wherein connection lines 605 are located over the wafer 110surface, but the shielding contact pads 505 are lacking, as illustratedin FIG. 11. In this case, during the test the shielding probes 205 willdirectly contact the connection lines 605.

According to a further embodiment of the present invention, instead ofhaving one connection line 605 per single die 102, a same connectionline 605 may be exploited for shielding more dies 102 at the same time.A first example of such an embodiment is illustrated in FIG. 12A,wherein each scribe line 150 is crossed by a single connection line 605,in such a way to form a grid structure; in the same way as previouslydescribed, such grid structure may be arranged over the passivationlayer covering the scribe lines 150 or under the wafer 110 surface. Afurther example of such solution is shown in FIG. 12B, wherein eachscribe line 150 includes more than one connection line 605, and eachconnection line 605 is used to shield more than one die 102 at the sametime.

In the previously described embodiments, each connection line 605 may bebiased by means of a voltage fed by the tester through a probe 135 whichis in a communication relationship with a contact pad 137—included in adie 102—connected to the connection line 605 itself. However, thepreviously described embodiments may be applied to the case in which theconnection lines 605 are not connected to any contact pad 137 locatedwithin a die 102, and the biasing voltage of the connection line 605 isfed by the tester through at least one of the shielding probes 205adapted to enter in communication relationship with such connection line605, as already outlined in reference with FIG. 8B. Such embodiments arevalid even if the shielding contact pads 505 are directly formed withinthe seal ring (not illustrated in figure) of the die 102 instead ofbeing formed in the scribe line 105. In this case, the metallicstructure of the seal ring functions as a connection line 605 as well,and thus such ring may be a closed loop or an open loop as in thepreviously discussed cases.

The embodiments of the present invention that have been described untilnow may allow efficiently reducing the crosstalk phenomenon among probes135 crossed by RF test signals destined to enter in communicationrelationship with contact pads 137 belonging to different die 102. Butthe electromagnetic shielding structures obtainable by means of theshielding probes 205 previously described may not allow reducing thecrosstalk phenomenon among probes 135 crossed by RF test signalsdestined to enter in communication relationship with contact pads 137belonging to the same die 102.

As a consequence, according to an embodiment of the present invention,each probe 135 adapted to be crossed by RF test signals during the testoperations may be surrounded by a corresponding electromagneticshielding structure adapted to shield the electromagnetic shieldirradiated by such probe 135. Particularly, according to an embodimentof the present invention, such electromagnetic shielding structure mayconsist of proper shielding probes 205 similar to those previouslydescribed.

For example, as illustrated in FIG. 13, each probe 135 adapted to becrossed by RF test signals may be surrounded by a connection line 605connected to shielding contact pads 505; similarly to what has beenpreviously described regarding the whole shielding of a die 102, duringthe test the shielding contact pads 505 are contacted by the shieldingprobes 205, properly biased by the tester through the probe card 105 orone of the shielding contact pads 505 connected to the connection line605. All that has been previously described may be applied to the caseof single shielding probe 135, such as for example the presence ofshielding contact pads 505 connected to more than one connection line605, connection lines 605 of the open loop type, connection lines 605lacking of contact pads 505 adapted to be directly contacted by theshielding probes 505, and so on. Given that by providing an RF testsignal to a generic contact pad 137 of a die 102 currents are generatedwithin the circuit integrated therein such to make the voltages of othercontact pads 137 of the same die 102 oscillate at the same frequency ofthe RF signal, which voltages would normally have to be kept constant(such as for example the one of a contact pad 137 adapted to receive theground voltage), the probes 135 connected to such contact pads as wellwould be crossed by an RF signal component, and thus they may irradiatein turn an electromagnetic field. As a consequence, according to anembodiment of the present invention, also the probes 135 destined toenter in communication relationship with such contact pads 137 may besurrounded by electromagnetic shielding structures such as the onespreviously described.

After the test operations and after the wafer 110 sorting, some of thepreviously described structures may be still present on the die 102, andthus they may be advantageously used for assembling the die 102 itselfin order to form at least one electromagnetic shield for at least onesignal that is received and/or transmitted from/to the die 102 to/froman external electronic system. For example the die 102 may be assembledon a PCB (not shown in any figure) and may be connected thereto by meansof conductive protrusions (in jargon, “bumps”) located over the contactpads 137 and 505. To this effect, all the considerations previouslydescribed for the contact pads 137 and 505 may be applied even if suchcontact pads are provided with bumps located thereon, which will contactthe probes 135 and 205.

According to a further embodiment of the present invention, theelectromagnetic shielding of the single probe 135 may be implemented onthe probe card 105 (and particularly on the substrate 130) by means ofstructures that are different than the previously described shieldingprobes 205. Particularly, considering a probe card 105 provided withprobes 135 of the MEMS type manufactured by means of lithographictechniques, it may be possible to create electromagnetic shieldingstructures made of conductive material during the same steps of theprobes 135 manufacturing process.

For example, as it is illustrated in the FIGS. 14A and 14B, a wall madeof a metallic material, identified with the reference 705, may beprovided within the space between two adjacent probes 135, which wallmay be directly connected to the lower surface of the substrate 130 fromwhich the probes 135 extends. As can be seen in FIG. 14A, the height ofsuch walls along the z axis—i.e., along the direction that isperpendicular to the surface of the substrate 130 facing the wafer 110to be tested—is sufficiently extended to allow substantial covering ofthe whole probe 135 when the latter is in contact relationship with acorresponding contact pad 137 on the die 102 to be tested. At the sametime, in order to allow the probe 135 to contact the correspondingcontact pad 137 in a correct manner, such extension is sufficientlyreduced so as to leave the probe 135 tip to protrude. Like the shieldingprobes 205, the walls 705 are biased to a constant potential (such asthe ground voltage) or to a slowly variable potential, for examplethrough the tester.

As it is illustrated in FIG. 14C, according to an embodiment of thepresent invention the walls 705 may close themselves so as to form aring entirely surrounding at least one probe 135 (in the figure, on theleft); according to an alternative embodiments of the present inventionsuch ring may be provided with several openings or may be interrupted inseveral portions (such as for the probe 135 on the right of the figure),or may have a different shape.

Naturally, in order to satisfy local and specific requirements, a personskilled in the art may apply to the above description many modificationsand alterations. Particularly, although one or more embodiments of thepresent invention have been described with a certain degree ofparticularity, it should be understood that various omissions,substitutions and changes in the form and details as well as otherembodiments are possible; moreover, it is expressly intended thatspecific elements and/or method steps described in connection with anydisclosed embodiment of the invention may be incorporated in any otherembodiment as a general matter of design choice.

1. A probe card comprising a plurality of probes, each probe beingadapted to contact a corresponding terminal of a circuit integrated inat least one die of a semiconductor material wafer during a test phaseof the wafer, said plurality of probes including at least one probeadapted to provide and/or receive a radio frequency test signal to/fromthe corresponding terminal during the test phase, said probe cardincludes at least one electromagnetic shield structure corresponding tothe at least one probe adapted to provide and/or receive the radiofrequency test signal for the at least partial shielding of anelectromagnetic field irradiated by such at least one probe adapted toprovide and/or receive the radio frequency test signal.
 2. The probecard according to claim 1, wherein the probes are connected to the probecard by means of a supporting element configured in such a way to face awafer surface during the test phase, said at least one shield structureextending from the supporting element toward the wafer surface.
 3. Theprobe card of claim 1, wherein said at least one shield structure isconductive.
 4. The probe card of claim 3, wherein said at least oneshield structure is configured to be biased with a shielding potential.5. The probe card of claim 4, wherein said shielding potential has aconstant value.
 6. The probe card of claim 4, wherein said shieldingpotential has a value that varies at a frequency that is substantiallylower than the frequency of the radio frequency test signal.
 7. Theprobe card of claim 1, wherein said at least one shield structurecomprises at least one test probe.
 8. The probe card of claim 7,wherein: said at least one die includes a plurality of dies arranged onthe wafer; the dies of each pair of adjacent dies on the wafer areseparated by means of a separating line, and said at least one testprobe comprises a plurality of test probes configured to be arrangedcorresponding to at least one separating line between two adjacent diesduring the test phase.
 9. The probe card of claim 7, wherein: such atleast one die includes a plurality of dies arranged on the wafer; thedies of each pair of adjacent dies on the wafer are separated by meansof a separating line, and said at least one test probe comprises aplurality of test probes configured to be arranged corresponding to theseparating lines around at least one die for surrounding at leastpartially such die during the test phase.
 10. The probe card of claim 8,wherein the test probes are configured to be arranged in contact withthe separating lines during the test phase.
 11. The probe card of claim8, wherein: said separating lines are provided with shielding contactpads, and the test probes are configured to be arranged in contact withthe shielding contact pads during the test phase.
 12. The probe card ofclaim 11, wherein: said separating lines are provided with conductiveconnection lines, and the test probes are configured to be arranged incontact with the conductive connection lines during the test phase. 13.The probe card of claim 11, wherein the shielding contact pads aredivided in groups, the shielding contact pads of each group beingconnected to each other by means of conductive connection lines in theseparating lines.
 14. The probe card of claim 12, wherein the probe cardis configured to be coupled with a tester that provides and/or receivesthe test signals during the test phase, said shielding potential beingprovided to the at least one shield structure by the tester through theprobe card.
 15. The probe card of claim 14, wherein said shieldingpotential is provided to the conductive connection lines by the testerthrough the probe card.
 16. An apparatus, comprising: a support; a firstprobe tip extending from the support; and an electromagnetic shieldextending from the support adjacent to the probe tip.
 17. The apparatusof claim 16 wherein: the first probe tip has a longitudinal axis; andthe electromagnetic shield at least partially surrounds the first probetime in a dimension that is substantially perpendicular to thelongitudinal axis.
 18. The apparatus of claim 16 wherein theelectromagnetic shield comprises multiple shield members.
 19. Theapparatus of claim 16 wherein: the first probe tip extends from thesupport a first distance; and the electromagnetic shield extends fromthe support a second distance that is less than the first distance. 20.The apparatus of claim 16 wherein the electromagnetic shield comprises asecond probe tip.
 21. The apparatus of claim 16, further comprising: anrf-signal node disposed on the support and coupled to the first probetip; a bias-signal node disposed on the support; and wherein theelectromagnetic shield comprises a second probe tip coupled to thebias-signal node.
 22. The apparatus of claim 16 wherein theelectromagnetic shield is electrically isolated from signal nodesdisposed on the support.
 23. The apparatus of claim 16 wherein theelectromagnetic shield comprises multiple second probe tips eachdisposed on a respective side of the first probe tip.
 24. The apparatusof claim 16, further comprising: wherein the first probe tip isconfigured to engage a contact area of an integrated-circuit die; andwherein the electromagnetic shield comprises a second probe tip that isconfigured to engage a contact area of a wafer scribe line adjacent tothe integrated-circuit die.
 25. The apparatus of claim 16, furthercomprising: wherein the first probe tip is configured to engage acontact area of a wafer scribe line adjacent to an integrated-circuitdie; and wherein the electromagnetic shield comprises a second probetime that is configured to engage a contact area of theintegrated-circuit die.
 26. The apparatus of claim 16, furthercomprising: wherein the first probe tip is configured to engage a firstcontact area of an integrated-circuit die; and wherein theelectromagnetic shield comprises a second probe tip that is configuredto engage a second contact area of the integrated-circuit die.
 27. Theapparatus of claim 16, further comprising: wherein the first probe tipis configured to engage a first contact area of a wafer scribe lineadjacent to an integrated-circuit die; and wherein the electromagneticshield comprises a second probe tip that is configured to engage asecond contact area of the wafer scribe line.
 28. The apparatus of claim16, further comprising: wherein the first probe tip is configured toengage a contact area of a wafer; and wherein the electromagnetic shieldcomprises a second probe tip that is configured to remain disengagedfrom the wafer.
 29. The apparatus of claim 16 wherein theelectromagnetic shield is electrically conductive.
 30. A system,comprising: probe assembly, comprising: a support; a first probe tipextending from the support; and an electromagnetic shield extending fromthe support adjacent to the probe tip; and a controller coupled to theprobe assembly.
 31. The system of claim 30 wherein the controller isoperable to generate an rf test signal on the first probe tip.
 32. Thesystem of claim 30 wherein the controller is operable to receive an rfresponse signal from the first probe tip.
 33. The system of claim 30wherein the controller is operable to generate a bias signal on theelectromagnetic shield.
 34. A wafer, comprising: a first contact areaoperable to engage a probe tip; and a second contact area operable toengage an electromagnetic shield.
 35. The wafer of claim 34, furthercomprising: a die; wherein the first contact area is disposed on thedie; and wherein the second contact area is disposed on the die.
 36. Thewafer of claim 34, further comprising: a die; a scribe line; wherein thefirst contact area is disposed on the die; and wherein the secondcontact area is disposed on the scribe line.
 37. The wafer of claim 34,further comprising: a die; a scribe line; wherein the first contact areais disposed on the scribe line; and wherein the second contact area isdisposed on the die.
 38. The wafer of claim 34, further comprising: ascribe line; wherein the first contact area is disposed on the scribeline; and wherein the second contact area is disposed on the scribeline.
 39. The wafer of claim 34, further comprising a third contact areacoupled to the second contact area and operable to receive a shield biassignal.
 40. The wafer of claim 34, further comprising: a die; whereinthe second contact area is disposed on the die; and a third contact areadisposed on the die and coupled to the second contact area.
 41. Thewafer of claim 34, further comprising: a die; a scribe line; wherein thesecond contact area is disposed on the die; and a third contact areadisposed on the scribe line and coupled to the second contact area. 42.The wafer of claim 34, further comprising: a die; a scribe line; whereinthe second contact area is disposed on the scribe line; and a thirdcontact area disposed on the die and coupled to the second contact area.43. The wafer of claim 34, further comprising: a scribe line; whereinthe second contact area is disposed on the scribe line; and a thirdcontact area disposed on the scribe line and coupled to the secondcontact area.
 44. The wafer of claim 34, further comprising: a surface;and wherein the second contact area comprises a conductor that at leastpartially surrounds the first contact area in a dimension substantiallyparallel to the surface.
 45. The wafer of claim 34, further comprising:a die; scribe lines adjacent to the die; and wherein the second contactarea comprises a conductor disposed in the scribe lines.
 46. The waferof claim 34 wherein the second contact area is operable to receive ashield bias signal from the electromagnetic shield.
 47. The wafer ofclaim 34 wherein the second contact area is operable to provide a shieldbias signal to the electromagnetic shield.
 48. A die, comprising: afirst contact area operable to engage a probe tip; and a second contactarea operable to engage an electromagnetic shield.
 49. A method,comprising: contacting a first contact region of a semiconductorstructure with a first signal probe; and contacting a second contactregion of the semiconductor structure with a first electromagneticshield.
 50. The method of claim 49, further comprising providing a testsignal to the first contact region via the first signal probe.
 51. Themethod of claim 49, further comprising receiving a test signal from thefirst contact region via the first signal probe.
 52. The method of claim49, further comprising biasing the electromagnetic shield via a biassource that is remote from the semiconductor structure.
 53. The methodof claim 49, further comprising biasing the electromagnetic shield viathe second contact region.
 54. The method of claim 49, furthercomprising: providing a bias signal to a third contact region of thesemiconductor structure; and coupling the bias signal from the thirdcontact region to the electromagnetic shield via the second contactregion and a conductive region of the semiconductor structure.
 55. Themethod of claim 49, further comprising: providing a bias signal to athird contact region of the semiconductor structure via a secondelectromagnetic shield; and coupling the bias signal from the secondelectromagnetic shield to the first electromagnetic shield via the thirdcontact region, a conductive region of the semiconductor structure, andthe second contact region.
 56. The method of claim 49, furthercomprising: contacting a third contact region with a secondelectromagnetic shield; providing a bias signal to the firstelectromagnetic shield; and coupling the bias signal from the firstelectromagnetic shield to the second electromagnetic shield via thesecond contact region, a conductive region of the semiconductorstructure, and the third contact region.